UVM Verification Engineer

The UVM Verification Engineer specializes in Universal Verification Methodology based projects. You will read more about it in this job descrition: tasks, educational background, skills, salary,…

Are you looking for a company specializing in FPGA/ASIC/SoC design verification to assist you in your project?

Read more about our digital design verification services and our analog mixed signal verification services, then do not hesitate to contact us, so that we can discuss about it together.

ELSYS is an ARM Approved Design Partner, a Microchip Authorized Design Partner and is member of the Xilinx Alliance Program. We have design centers in Europe (France), Eastern Europe (Serbia) and a branch in the USA (California, in the Silicon Valley).

Contents:

Methodology
Roles and Responsibilities
Educational background
Skills
Salary
Jobs

UVM Universal Verification Methodology

Universal Verification Methodology (UVM) is a standardized methodology for verification of integrated circuit, ASIC, and SoC designs.

It is largely derived from the Open Verification Methodology (OVM).

The UVM class library brings some automation to the SystemVerilog language, such as sequences and data automation functions.

The UVM method was developed by the Accellera Systems Initiative, with the support of several companies including Cadence, Mentor Graphics and Synopsys.

What does an UVM engineer do?

The UVM Verification Engineer is involved in FPGA, System-on-Chip, Integrated Circuit or ASIC design projects.

His / her main tasks are:

Analyse the specification to learn about the system.
Develop the audit plan / test strategy. This can, for example, take the form of a table listing the test number, its title, the name of the function covered, its description, whether it is a unit test or intended to validate the system environment etc.
Validate the verification plan with the team leader and / or designer.
Set up a UVM verification environment;
Develop test benches in SystemVerilog.
Write scripts to automate test procedures.
Perform regular non-regression tests.
Analyse the results and write the test reports. The information is then sent to the designer so that he can correct the bugs.

Projects often have an international dimension, with engineers in Europe, the United States and Asia.

How to become an UVM Verification Engineer?

It is essential to have completed a digital electronics training course at a University or an engineering school (master’s degree), and ideally to have at least a first significant experience in ASIC or FPGA verification.

Skills

The skills of a UVM verification engineer usually sought are:

Design in VHDL / Verilog.
Practice of SystemVerilog.
Flow Control Simulation / Synthesis / Routing.
Practical experience of the UVM methodology.
Mastering Python, Perl, Bash scripting …
Practice of configuration management (Git, SVN, ClearCase).
For non-native English speakers, written and oral English.

Humanly, you have to be rigorous and have a good analytical mind; ideally, you need a system vision that allows you to take complex designs into account.

Finally, you have to enjoy working in a team and being a good communicator.

Salary

In France, a young UVM Verification Engineer can expect a salary between 33K€ and 36K€.